1. Field of the Invention
The present invention relates to a wafer level packaging method. More particularly, the present invention relates to a wafer level packaging cap used for the packaging method, and a fabrication method thereof.
2. Description of the Related Art
Generally, minute structures manufactured in a chip unit such as an RF filter, a communication-use RF switch and an RF MEMS, and particular function-performing devices such as an actuator, are vulnerable to water, other particles and high temperature, accordingly requiring packaging.
The packaging is performed by covering and sealing up an upper surface of a device wafer formed with the particular function-performing device, with a cap formed having a predetermined cavity offering a space to house the device.
A wafer level packaging is to seal up a wafer having a plurality of devices, with a packaging cap formed in a wafer unit, before cutting the wafer in a chip unit.
The device wafer includes a device substrate, a particular function-performing device formed on an upper surface of the device substrate and a plurality of device pads electrically connected to the device. The device wafer is manufactured through a general semiconductor manufacturing process.
The packaging cap includes: a cap substrate having a predetermined of cavity housing the device on a lower surface thereof, and joined with the device wafer; a plurality of first metal lines formed on the lower surface of the cap substrate, corresponding to a plurality of device pads electrically connected to the device; a plurality of second metal lines corresponding to the first metal lines and formed inward of the cavity from the lower surface of the cap surface; a plurality of connection holes penetrating upwardly in the cap substrate, corresponding to the second metal lines respectively; a plurality of connection units formed inside the connection holes and electrically connected to the second metal lines; and a plurality of cap pads formed on the upper surface of the cap substrate and electrically connected to a plurality of upper parts of the connection units.
The packaging is completed by bonding the device wafer and the packaging cap by use of sealing lines formed thereon.
Referring to FIGS. 1A through 1E, the packaging cap fabrication method will be described hereinafter.
As illustrated in FIG. 1A, a wafer 10 is provided to act as the cap substrate of the packaging cap. A cavity is created on a lower surface of the wafer 10 through a predetermined process. A seed metal is deposited to cover a surface of the cavity and the lower surface of the wafer 10, in order to form a seed layer 11.
As illustrated in FIG. 1B, an upper surface of the wafer 10; that is, a reverse surface to a seed layer-formed surface, is mask-patterned and dry-etched by use of induced coupled plasma ion etching device (ICP-RIE) until completely penetrating the wafer 10, to process a connection hole 10a. 
Through an ashing process, a mask used to form the pattern (not shown) of the connection hole 10a is removed. As illustrated in FIG. 1C, a metal is deposited in the connection hole 10a by plating it with metal material from the seed layer 11 on the bottom of the connection hole 10a, in order to form a plurality of connection units 12. The connection units 12 go through lapping and chemical mechanical planarization (CMP) processes to make their different heights uniform and then they are cleaned.
The metal is deposited on the upper surface of the wafer 10, and patterned through a photolithography process. As illustrated in FIG. 1D, a cap pad 13 is formed to electrically connect to the connection unit 12.
The seed layer 11 on the lower surface of the wafer 10 is formed with a first metal line (11′ of FIG. 1D) by use of the photolithography process. The lower surface of the wafer 10 is formed with a second metal line 14 connected to the first metal line 11′, and a sealing line 15. The sealing line 15 is used to package the device substrate during the packaging process.
As illustrated in FIG. 1E, the completed packaging cap 1 covers an upper part of a device wafer 2.
However, the packaging cap manufactured through the above-described process has the following problems. The wafer needs to be thick to prevent any possible loss or damage to the wafer during processing, accordingly increasing the package size.
The connection holes of the wafer need to penetrate the wafer, inconveniently requiring a long processing time. That is, common silicon (Si) wafer which is used as the cap substrate has a difficulty in lowering the thickness of the cap substrate to 300 μm or less, due to the inconvenience in processing of the Si. Accordingly, it is hard to save unit costs.
The connection hole which penetrates the wafer requires a longer time for plating metal materials in deep connection holes and thus increases the entire costs.
The connection holes formed on the cap substrate are directly plated with the metal materials, so the metal materials fail to be firmly attached to the holes, dropping electric stability.